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Silicon Labs /BGM240PB32VNA /CMU_S /EUSART0CLKCTRL

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Interpret as EUSART0CLKCTRL

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/CMU_NS/EUSART0CLKCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CLKSEL

CLKSEL=DISABLED

Description

No Description

Fields

CLKSEL

Clock Select

0 (DISABLED): EUSART0 is not clocked

1 (EM01GRPCCLK): EM01GRPCCLK is clocking EUSART0

2 (HFRCOEM23): HFRCOEM23 is clocking EUSART0

3 (LFRCO): LFRCO is clocking EUSART0

4 (LFXO): LFXO is clocking EUSART0

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data